Referring to the current flip-chip technique, electrode pads are located on a surface of a semiconductor integrated circuit (IC) chip and a corresponding pad is provided on an organic circuit board. Solder bumps or other conductively adhesive materials are mounted on an active surface of the chip, which is provided on the top of the circuit board, such that the solder bump or other conductively adhesive material can be used as input/output connections for electrically and mechanically connecting the chip to the circuit board.
Referring to FIG. 1 which demonstrates a flip chip element known in the prior-art, a plurality of metal bumps 11 is formed on an electrode pad 12 of a chip 13, and a plurality of solder bumps 14 made of solder materials is formed on a pad 15 of an organic circuit board 16. Under a reflow temperature condition in which the solder bump 14 can be melted, the solder bump 14 is subject to a reflow process to make contact with a corresponding metal bump 11, so as to form a joint 17. Referring to a solder bump joint, a bottom cement material 18 such as underfill can be further filled in a gap between the chip and the circuit board, such that a thermal expansion difference existed between the chip 13 and the circuit board 16 can be prevented and a stress of the joint 17 can be reduced.
Recently, the solder material is deposited on the pad of the circuit board to form the solder bump by stencil printing technology. Referring to FIG. 2, the currently used stencil printing technology mainly provides a circuit board 20 having a solder mask layer 21 such as green paint on a surface thereof, and a plurality of pads 22 for forming locations of solder materials (not shown) such as solder pastes. Firstly, a stencil 23 having a plurality of grids 23a is provide on the circuit board 20. After coating the stencil 23 with the solder material, a roller 24 is repeatedly rolled on the stencil 23 or a spraying process is performed, such that the solder material is able to form a solder (not shown) on the pad using the gird 23a of the stencil 23 after the removal of the stencil 23. Subsequently, under a reflow temperature condition in which the solder can be melted, the solder is subject to a reflow process to form a solder bump on the pad of the substrate. Furthermore, the stencil of the foregoing stencil printing technology is preferably a steel plate.
During practical operation, along with the blooming development of various portable products in the fields of communication, networking and computing, packages such as ball grid array (BGA), flip chip, chip size package (CSP) and multi chip module (MCM) which are characterized with a miniaturized integrated circuit (IC) area, a high density and multiple legs have become the mainstream of the packaging market. Highly effective chips such as a microprocessor, a chip set and a drawing chip are usually combined with the foregoing package to achieve an operating function of a higher speed. However, circuits on a substrate and a dimension of a pad must be miniaturized for such structures to be applied. When the dimension of the pad and pitches are miniaturized, openings formed penetrating through the stencil also need to be reduced. Thus, a cost of stencil fabrication cannot be reduced due to difficulties in performing mold opening of the stencil. Also, it is of difficulties to allow the solder material to pass through the opening due to smallness of the opening.
Furthermore, referring to criteria on the production accuracy of the solder material, frequencies and cleanness of stencil printing have to be concerned in addition to a precise dimension of the stencil while performing the stencil printing technology. As the number of printings is increased, the solder material remained in a wall of the opening of the stencil is as well accumulated. Since the solder material is of a certain viscosity, the amount and shape of the solder material for performing next printing will be different from the specification if the solder material is previously accumulated. Therefore, the stencil has to be wiped out after performing a certain number of printings to ensure the cleanness of the stencil during practical operation, otherwise the shape and dimension of the solder material might be altered to cause an inconvenience as well as a decreased reliability in fabrication.
Referring to Taiwan Patent No. 508987 entitled “Method for fabricating solder on organic circuit board using electroplating process”, a solder material can be formed on an opening area of a mask layer using an electroplating process. First of all, an organic circuit board having at least a pad is provided. An insulating layer is coated on the circuit board to expose the foregoing pad. Subsequently, a thin metal layer serving as a current conductive path is formed on the circuit board, and an electroplating resist layer is formed with a plurality of openings on the thin metal layer to expose the pads. A solder material is formed in the opening of the electroplating resist layer using an electroplating process prior to successively remove the electroplating resist layer and the thin metal layer being covered underneath the electroplating resist layer.
Although the foregoing method is able to eliminate drawbacks in the prior-art stencil printing technology, the procedures are very complex and the cost is very high. Also, when the solder material is formed on the pad using the electroplating process, the thin metal layer serving as the current conductive path might be affected by the electroplating resist layer located above the conductive layer, therefore contaminating the pad, the conductive layer and the fabricated solder material. Additionally, in order to form sufficient solder materials on the pad using the electroplating process, the criteria on the characteristics and thickness of the electroplating resist layer is very stringent, such that the fabrication is complicated as a consequence. Finally, during the subsequent removal of the electroplating resist layer, the fabricated solder material formed in the electroplating resist layer might be influenced to cause a reliability problem.